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RTL Design Sherpa CocoTB Framework · Verification Infrastructure for RTL Testing
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Wishbone B4 Components Index

The Wishbone B4 (pipelined) family: a master, a slave over a memory model, a monitor with the protocol checks, a packet class, sequences for describing traffic, and the factories that wire them up.

Overview

  • Overview - What the family covers, how it differs from a GAXI composition, timing convention

Core Components

  • wb4_components.py - WB4Monitor, WB4Slave, WB4Master on the cocotb_bus chassis
  • wb4_packet.py - WB4Packet: one request and its termination
  • wb4_sequence.py - WB4Sequence: the traffic axis, with address windows for the ERR/RTY ranges
  • wb4_factories.py - create_wb4_master / create_wb4_slave / create_wb4_monitor
  • shared/wb4_common.py - signal sets, data-name aliases, the status encoding